{"id":1083,"date":"2026-01-19T06:05:27","date_gmt":"2026-01-19T06:05:27","guid":{"rendered":"https:\/\/template01.zehannet.net\/?p=1083"},"modified":"2026-01-19T06:05:28","modified_gmt":"2026-01-19T06:05:28","slug":"what-are-the-most-common-pcb-design-mistakes-that-cause-manufacturing-delays","status":"publish","type":"post","link":"https:\/\/template01.zehannet.net\/ar\/what-are-the-most-common-pcb-design-mistakes-that-cause-manufacturing-delays\/","title":{"rendered":"What are the most common PCB design mistakes that cause manufacturing delays?"},"content":{"rendered":"<div class=\"wp-block-rank-math-toc-block\" id=\"rank-math-toc\"><h2>Table of Contents<\/h2><nav><ul><li><a href=\"#common-pcb-design-mistakes-that-delay-pcb-manufacturing\">Common PCB design mistakes that delay PCB manufacturing<\/a><\/li><li><a href=\"#don-t-involve-the-fabricator-early\">Don\u2019t involve the fabricator early<\/a><\/li><li><a href=\"#over-spec-ing-tight-trace-space-via-tolerances\">Over-spec\u2019ing tight trace\/space\/via tolerances<\/a><\/li><li><a href=\"#incomplete-or-unclear-stack-up-details\">Incomplete or unclear stack-up details<\/a><\/li><li><a href=\"#solder-mask-design-errors\">Solder mask design errors<\/a><\/li><li><a href=\"#silkscreen-problems\">Silkscreen problems<\/a><\/li><li><a href=\"#mechanical-constraints-aren-t-defined-clearly\">Mechanical constraints aren\u2019t defined clearly<\/a><\/li><li><a href=\"#manufacturing-data-package-is-inconsistent\">Manufacturing data package is inconsistent<\/a><\/li><li><a href=\"#ignore-component-lifecycle-availability\">Ignore component lifecycle \/ availability<\/a><\/li><li><a href=\"#practical-scenarios-that-match-how-delays-really-happen\">Practical scenarios that match how delays really happen<\/a><\/li><li><a href=\"#a-simple-way-to-reduce-manufacturing-delays\">A simple way to reduce manufacturing delays<\/a><\/li><\/ul><\/nav><\/div>\n\n\n\n<p>If you\u2019ve ever sent a \u201cclean\u201d PCB design to a factory and still got stuck in&nbsp;<strong>CAM hold<\/strong>, you\u2019re not alone. The board didn\u2019t \u201cfail.\u201d It just hit a spot where the fab or SMT line can\u2019t move forward without asking questions, rerunning checks, or waiting for missing info.<\/p>\n\n\n\n<p>We build boards for OEMs, EMS teams, design houses, labs, and startups that need fast prototyping and stable volume runs. That\u2019s the whole point of a&nbsp;<strong>China PCB B2B factory<\/strong>&nbsp;like ours: quick-turn prototypes, reliable assembly, tight QC, and on-time delivery worldwide. You can see the full service map on our&nbsp;<a href=\"https:\/\/template01.zehannet.net\/ar\/\">homepage<\/a>.<\/p>\n\n\n\n<p>Below are the most common design-side mistakes that slow manufacturing down, plus what to do instead. The internal links in this article come from your PCB.json list.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"960\" height=\"720\" src=\"https:\/\/template01.zehannet.net\/wp-content\/uploads\/2026\/01\/What-are-the-most-common-PCB-design-mistakes-that-cause-manufacturing-delays-1.jpg\" alt=\"What are the most common PCB design mistakes that cause manufacturing delays\" class=\"wp-image-1085\" title=\"\" srcset=\"https:\/\/template01.zehannet.net\/wp-content\/uploads\/2026\/01\/What-are-the-most-common-PCB-design-mistakes-that-cause-manufacturing-delays-1.jpg 960w, https:\/\/template01.zehannet.net\/wp-content\/uploads\/2026\/01\/What-are-the-most-common-PCB-design-mistakes-that-cause-manufacturing-delays-1-600x450.jpg 600w, https:\/\/template01.zehannet.net\/wp-content\/uploads\/2026\/01\/What-are-the-most-common-PCB-design-mistakes-that-cause-manufacturing-delays-1-300x225.jpg 300w, https:\/\/template01.zehannet.net\/wp-content\/uploads\/2026\/01\/What-are-the-most-common-PCB-design-mistakes-that-cause-manufacturing-delays-1-768x576.jpg 768w\" sizes=\"auto, (max-width: 960px) 100vw, 960px\" \/><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"common-pcb-design-mistakes-that-delay-pcb-manufacturing\">Common PCB design mistakes that delay PCB manufacturing<\/h2>\n\n\n\n<p>Here\u2019s the quick scan. If your project keeps slipping, this table usually tells you why.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><thead><tr><th>Mistake (DFM\/DFA keyword)<\/th><th>Where the delay happens<\/th><th>What the factory typically does<\/th><th>What you should send \/ change<\/th><\/tr><\/thead><tbody><tr><td>Don\u2019t involve the fabricator early<\/td><td>Quoting + CAM review<\/td><td>Puts job on hold, raises EQs<\/td><td>Share constraints early, align capabilities and targets<\/td><\/tr><tr><td>Over-spec\u2019ing tight trace\/space\/via tolerances<\/td><td>CAM tooling + process planning<\/td><td>Routes to special process or rejects rules<\/td><td>Use standard capability unless performance truly demands more<\/td><\/tr><tr><td>Incomplete or unclear stack-up details<\/td><td>Stack-up approval + impedance setup<\/td><td>Stops for clarification, suggests a new build<\/td><td>Provide full stack-up with materials, copper, dielectric, impedance notes<\/td><\/tr><tr><td>Solder mask design errors<\/td><td>Solder mask film + SMT yield<\/td><td>Flags mask issues, risks rework<\/td><td>Keep mask clearances sane, avoid bad dams, tent vias when needed<\/td><\/tr><tr><td>Silkscreen problems<\/td><td>SMT setup + inspection<\/td><td>Slows line for manual checks<\/td><td>Keep legend off pads, add polarity + pin-1 marks<\/td><\/tr><tr><td>Mechanical constraints aren\u2019t defined clearly<\/td><td>Routing + depanelization<\/td><td>Requests drawings, revises panel plan<\/td><td>Define cutouts, slots, tolerance, V-score keepouts, rails<\/td><\/tr><tr><td>Manufacturing data package is inconsistent<\/td><td>CAM import + drill programming<\/td><td>Stops to reconcile files<\/td><td>Single revision set: Gerber\/X2, drill, stack-up, fab notes<\/td><\/tr><tr><td>Ignore component lifecycle \/ availability<\/td><td>Purchasing + kitting<\/td><td>Pauses build, triggers BOM scrub<\/td><td>Check AVL, lifecycle, alternates, and packaging upfront<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>Now let\u2019s break them down with real shop-floor scenarios.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"don-t-involve-the-fabricator-early\">Don\u2019t involve the fabricator early<\/h2>\n\n\n\n<p>This one looks harmless, but it\u2019s a repeat offender in NPI. You design to \u201cwhat you\u2019ve always used,\u201d then you send files, then you wait. The fab comes back with an EQ list: \u201cCan you confirm copper weight?\u201d \u201cIs this via tented?\u201d \u201cDo you really need this impedance tolerance?\u201d That back-and-forth is pure schedule burn.<\/p>\n\n\n\n<p>A practical way to avoid it: treat your fab like part of your engineering team. Share constraints before you lock the layout. If you\u2019re doing a tougher build, route it through an advanced review early. Our&nbsp;<a href=\"https:\/\/template01.zehannet.net\/ar\/services\/advanced-pcb\/\">Advanced PCB service<\/a>&nbsp;is built for that kind of pre-check.<\/p>\n\n\n\n<p><strong>Where it shows up most<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>HDI fine-pitch boards with tight annular ring or microvia rules<\/li>\n\n\n\n<li>Mixed-material stacks (RF + FR-4)<\/li>\n\n\n\n<li>Rigid-flex with bend areas and stiffeners<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"960\" height=\"720\" src=\"https:\/\/template01.zehannet.net\/wp-content\/uploads\/2026\/01\/What-are-the-most-common-PCB-design-mistakes-that-cause-manufacturing-delays-2.jpg\" alt=\"What are the most common PCB design mistakes that cause manufacturing delays\" class=\"wp-image-1084\" title=\"\" srcset=\"https:\/\/template01.zehannet.net\/wp-content\/uploads\/2026\/01\/What-are-the-most-common-PCB-design-mistakes-that-cause-manufacturing-delays-2.jpg 960w, https:\/\/template01.zehannet.net\/wp-content\/uploads\/2026\/01\/What-are-the-most-common-PCB-design-mistakes-that-cause-manufacturing-delays-2-600x450.jpg 600w, https:\/\/template01.zehannet.net\/wp-content\/uploads\/2026\/01\/What-are-the-most-common-PCB-design-mistakes-that-cause-manufacturing-delays-2-300x225.jpg 300w, https:\/\/template01.zehannet.net\/wp-content\/uploads\/2026\/01\/What-are-the-most-common-PCB-design-mistakes-that-cause-manufacturing-delays-2-768x576.jpg 768w\" sizes=\"auto, (max-width: 960px) 100vw, 960px\" \/><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"over-spec-ing-tight-trace-space-via-tolerances\">Over-spec\u2019ing tight trace\/space\/via tolerances<\/h2>\n\n\n\n<p>Design teams often \u201cplay it safe\u201d by tightening rules. Ironically, that can slow you down more than it helps. If you spec ultra-tight trace\/space or tiny drills without a real need, CAM has to push the job into a narrower process window. That can mean special tooling, extra coupons, extra inspection steps, or a capability review.<\/p>\n\n\n\n<p>Think of it like ordering a custom part when a standard one works. The factory can do it, but the line won\u2019t sprint.<\/p>\n\n\n\n<p><strong>Fix that actually works<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Start with the fab\u2019s standard capability, then tighten only the nets that need it<\/li>\n\n\n\n<li>Keep via sizes and aspect ratios reasonable unless density forces your hand<\/li>\n\n\n\n<li>Call out the true requirement (signal integrity or creepage), not a blanket \u201cas small as possible\u201d<\/li>\n<\/ul>\n\n\n\n<p>If you\u2019re not sure what\u2019s standard, check our&nbsp;<a href=\"https:\/\/template01.zehannet.net\/ar\/capabilities\/\">Capabilities<\/a>&nbsp;page and align your rules to what\u2019s realistic for your board class.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"incomplete-or-unclear-stack-up-details\">Incomplete or unclear stack-up details<\/h2>\n\n\n\n<p>A missing stack-up is like shipping a recipe without ingredient amounts. The board might still get built, but the fab can\u2019t commit without guessing. That\u2019s why stack-up ambiguity triggers delays fast.<\/p>\n\n\n\n<p>This gets even more serious when you need impedance control. Without dielectric thickness, material type, copper weight, and target impedance, CAM can\u2019t finalize the build. They stop, ask questions, then re-run calculations after you answer.<\/p>\n\n\n\n<p><strong>What to include in your stack-up package<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Layer count and each layer name (L1, L2, etc.)<\/li>\n\n\n\n<li>Copper weights per layer (not just \u201c1 oz typical\u201d)<\/li>\n\n\n\n<li>Dielectric thicknesses and material family<\/li>\n\n\n\n<li>Impedance targets and which nets need them<\/li>\n\n\n\n<li>Any special notes: backdrill, via-in-pad, resin plug, filled vias<\/li>\n<\/ul>\n\n\n\n<p>If you\u2019re doing RF or high-speed, our&nbsp;<a href=\"https:\/\/template01.zehannet.net\/ar\/services\/pcb-fabrication\/\">PCB fabrication<\/a>&nbsp;flow is set up to review stack-up and impedance notes early, so you don\u2019t burn time after release.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"solder-mask-design-errors\">Solder mask design errors<\/h2>\n\n\n\n<p>Solder mask mistakes don\u2019t just cause defects. They also cause delays because the factory either needs you to approve changes or they need to rework a risky build plan.<\/p>\n\n\n\n<p>Two common triggers:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Mask slivers \/ weak dams<\/strong>\u00a0between tight-pitch pads<\/li>\n\n\n\n<li><strong>Mask over pads<\/strong>\u00a0because the opening is too small or misaligned<\/li>\n<\/ul>\n\n\n\n<p>In fine-pitch footprints, a tiny mask issue can snowball into solder bridging, tombstoning, or ugly rework. Nobody wants that on a B2B run.<\/p>\n\n\n\n<p><strong>Quick DFM habits<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Keep solder mask clearances consistent and manufacturable<\/li>\n\n\n\n<li>Avoid giant \u201cgang openings\u201d unless you truly need them<\/li>\n\n\n\n<li>For vias near pads, decide: tent, plug, or leave open, then document it<\/li>\n<\/ul>\n\n\n\n<p>If your project needs assembly too, align mask rules with your assembler\u2019s preferences. Our&nbsp;<a href=\"https:\/\/template01.zehannet.net\/ar\/services\/pcb-assembly\/\">PCB assembly<\/a>&nbsp;team sees mask-driven yield losses all the time, so we push these checks early.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"silkscreen-problems\">Silkscreen problems<\/h2>\n\n\n\n<p>Silkscreen feels cosmetic until it breaks the line. When legend text lands on pads, blocks fiducials, or hides polarity marks, SMT setup slows down. Operators then do manual verification. AOI becomes less confident. Debug takes longer.<\/p>\n\n\n\n<p>This is especially painful on:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Dense connector boards where pin-1 is hard to spot<\/li>\n\n\n\n<li>High-mix production where setup time matters<\/li>\n\n\n\n<li>Field-service products where technicians need readable labels<\/li>\n<\/ul>\n\n\n\n<p><strong>What good silkscreen does<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Clear polarity and pin-1 marks<\/li>\n\n\n\n<li>Reference designators that survive reflow<\/li>\n\n\n\n<li>Legible text size and spacing<\/li>\n\n\n\n<li>No legend on copper pads<\/li>\n<\/ul>\n\n\n\n<p>If you want to see how we handle inspection and marking consistency, our&nbsp;<a href=\"https:\/\/template01.zehannet.net\/ar\/quality\/\">Quality<\/a>&nbsp;page explains the checkpoints that protect shipment dates.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"mechanical-constraints-aren-t-defined-clearly\">Mechanical constraints aren\u2019t defined clearly<\/h2>\n\n\n\n<p>Mechanical ambiguity creates classic \u201ccan\u2019t ship it yet\u201d moments. The fab might not know whether a slot needs plating, how tight the outline tolerance is, or where copper must keep away from a V-score. That\u2019s how you end up with CAM questions, panel redesign, or a request for updated drawings.<\/p>\n\n\n\n<p><strong>Real-world example<\/strong>&nbsp;You design a control board that needs clean edges for a plastic housing. The outline includes tight corners, a few cutouts, and edge connectors. If you don\u2019t specify depanel method, rail needs, and keepouts, the panel plan changes midstream. That\u2019s delay plus risk.<\/p>\n\n\n\n<p><strong>What to define<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Outline, slots, cutouts, and plating requirements<\/li>\n\n\n\n<li>Edge connector bevel needs (if any)<\/li>\n\n\n\n<li>V-score or mouse-bite preference<\/li>\n\n\n\n<li>Copper-to-edge keepout rules<\/li>\n\n\n\n<li>Panel rails, tooling holes, and fiducials if you want consistent assembly<\/li>\n<\/ul>\n\n\n\n<p>For production-style builds, it helps to align these with the factory\u2019s process from day one.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"manufacturing-data-package-is-inconsistent\">Manufacturing data package is inconsistent<\/h2>\n\n\n\n<p>This is the fastest path to a hard stop. If the drill chart doesn\u2019t match the drill file, or layers don\u2019t line up with fab notes, CAM can\u2019t trust the dataset. They pause, then ask you to confirm which revision is \u201creal.\u201d<\/p>\n\n\n\n<p>This usually happens after a late ECO:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>You updated the PCB layout<\/li>\n\n\n\n<li>You forgot to regenerate NC drill<\/li>\n\n\n\n<li>Someone exported Gerbers from a different branch<\/li>\n\n\n\n<li>The stack-up PDF doesn\u2019t match the final constraints<\/li>\n<\/ul>\n\n\n\n<p><strong>Release checklist that prevents CAM hold<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>One revision label across Gerber, drill, drawings, stack-up, and notes<\/li>\n\n\n\n<li>Include readme with layer mapping and finish requirements<\/li>\n\n\n\n<li>Use consistent naming and avoid \u201cfinal_final2\u201d chaos<\/li>\n\n\n\n<li>Verify drill units, tool sizes, and plated vs non-plated holes<\/li>\n<\/ul>\n\n\n\n<p>If you\u2019re sending your first build, our&nbsp;<a href=\"https:\/\/template01.zehannet.net\/ar\/services\/\">Services<\/a>&nbsp;page shows the typical deliverables we expect for a clean release.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"ignore-component-lifecycle-availability\">Ignore component lifecycle \/ availability<\/h2>\n\n\n\n<p>Sometimes the PCB is perfect, but the build still stalls because parts can\u2019t be sourced. Obsolete parts, long lead-time passives, odd packaging, or missing alternates can pause kitting. Then the assembly slot slips, and your shipping date slips with it.<\/p>\n\n\n\n<p>This hits B2B buyers hard because your customer often needs stable supply for OEM rollout or a maintenance batch.<\/p>\n\n\n\n<p><strong>BOM habits that keep the line moving<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Check lifecycle status early<\/li>\n\n\n\n<li>Use an AVL and list alternates for risk parts<\/li>\n\n\n\n<li>Confirm package type (reel, tray, cut tape)<\/li>\n\n\n\n<li>Watch for parts with strict date code or traceability needs<\/li>\n<\/ul>\n\n\n\n<p>If you need a one-stop flow for prototypes through volume, our&nbsp;<a href=\"https:\/\/template01.zehannet.net\/ar\/products\/\">Products<\/a>&nbsp;section shows board types we commonly support, including high-density and control boards.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"practical-scenarios-that-match-how-delays-really-happen\">Practical scenarios that match how delays really happen<\/h2>\n\n\n\n<p>Here are three patterns we see across OEM, EMS, and design teams:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Startup prototype sprint<\/strong>: Tight deadlines, fast ECOs. The biggest risk is an inconsistent data package and missing stack-up notes. If you\u2019re doing quick-turn, start with a clean prototype flow like our\u00a0<a href=\"https:\/\/template01.zehannet.net\/ar\/b2b-custom-pcb-board-prototype-manufacturing-service-factory\/\">PCB prototype manufacturing service<\/a>.<\/li>\n\n\n\n<li><strong>Industrial control volume<\/strong>: The line hates ambiguity. Mechanical callouts, panel rules, and silkscreen clarity matter because rework kills throughput.<\/li>\n\n\n\n<li><strong>RF \/ high-speed board<\/strong>: Over-tight tolerances and vague impedance notes cause the most CAM churn. Build the stack-up first, then route the layout to match it.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"a-simple-way-to-reduce-manufacturing-delays\">A simple way to reduce manufacturing delays<\/h2>\n\n\n\n<p>You don\u2019t need magic. You need fewer surprises.<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Lock the stack-up before you route critical nets<\/li>\n\n\n\n<li>Spec only what you truly need<\/li>\n\n\n\n<li>Release one consistent file set<\/li>\n\n\n\n<li>Run DFM + DFA as a habit, not a rescue step<\/li>\n\n\n\n<li>If your design is tricky, involve the factory early<\/li>\n<\/ol>\n\n\n\n<p>If you want your next build to move without the \u201cCAM hold\u201d email, use our&nbsp;<a href=\"https:\/\/template01.zehannet.net\/ar\/contact-us\/\">Contact Us<\/a>&nbsp;page and send your stack-up + Gerbers + BOM. We\u2019ll tell you what will slow it down, and we\u2019ll tell you how to fix it before it hits the line.<\/p>","protected":false},"excerpt":{"rendered":"<p>PCB builds stuck on CAM hold? See common design mistakes\u2014stack-up gaps, over-tight rules, solder mask slips, and mismatched files\u2014plus fixes to ship on time.<\/p>","protected":false},"author":1,"featured_media":1085,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_gspb_post_css":"","footnotes":""},"categories":[1],"tags":[746,599,626,744,739,745],"class_list":["post-1083","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-market-trends","tag-cam-hold","tag-pcb-assembly","tag-pcb-dfm","tag-pcb-manufacturing-delays","tag-pcb-stack-up","tag-solder-mask"],"blocksy_meta":[],"_links":{"self":[{"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/posts\/1083","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/comments?post=1083"}],"version-history":[{"count":1,"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/posts\/1083\/revisions"}],"predecessor-version":[{"id":1086,"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/posts\/1083\/revisions\/1086"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/media\/1085"}],"wp:attachment":[{"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/media?parent=1083"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/categories?post=1083"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/template01.zehannet.net\/ar\/wp-json\/wp\/v2\/tags?post=1083"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}